A digital DLL circuit generates an internal clock signal by delaying the phase of an external clock signal. For example, a digital DLL circuit generates an internal clock signal delayed by one fourth of a cycle from an external clock signal to reduce jitter in the internal clock signal.
FIG. 1 shows the basic principle of a digital DLL circuit. The digital DLL circuit includes a phase determination section 1 and a phase adjustment section 2. The phase determination section 1 includes a delay generation unit 13, a stage quantity control unit 5, and a determination circuit 6. The delay generation unit 13 includes a plurality of buffer circuits (delay elements) 3, which are coupled in series, and a plurality of switch circuits 4, which are coupled between the input and output terminals of different buffer circuits 3.
The quantity of stages of the buffer circuits 3 that are coupled in series is selected by controlling the opening and closing of the plurality of switch circuits 4 with selection signals Sla0 to Slan, which are provided from the stage quantity control unit 5.
An external clock signal CLK is provided to the buffer circuit 3 in the first stage, and a clock signal (delay clock signal) CLK-D is provided from the buffer circuit 3 in the last stage or the switch circuit 4 in the last stage to the determination circuit 6. The determination circuit 6 is also provided with the external clock signal CLK.
The determination circuit 6 compares the phase of the external clock signal CLK and the phase of the delay clock signal CLK-D and provides a phase adjustment signal PC to the stage quantity control unit 5 so that the phase of the clock signal CLK-D is delayed by one cycle from the external clock signal CLK.
As shown in FIG. 2, if the phase difference of the clock signal CLK-D from the external clock signal CLK is less than one cycle (“CLK-D1” in FIG. 2), the stage quantity control unit 5 controls the opening and closing of the switch circuit 4 based on the phase adjustment signal PC to increase the quantity of stages of the buffer circuits 3 coupled in series. This lengthens the delay time of the clock signal CLK-D1.
If the phase difference of the clock signal CLK-D from the external clock signal CLK exceeds one cycle (“CLK-D3” in FIG. 2), the stage quantity control unit 5 reduces the quantity of stages of the buffer circuits 3 based on the phase adjustment signal PC. This shortens the delay time of the clock signal CLK-D3.
As a result of such an operation, the clock signal CLK-D converges to a clock signal CLK-D2 that is delayed by one cycle from the external clock signal CLK.
The stage quantity control unit 5 generates selection signals Slb0 to Slbn from the selection signals Sla0 to Slan in accordance with a phase amount set by a PHASE SET signal. The selection signals Sla0 to Slan are multiplied by a ratio that is in accordance with one fourth of a cycle to convert the selection signals Slb0 to Slbn to the selection signals Sla0 to Slan.
The phase adjustment section 2 includes a plurality of buffer circuits 7, which are coupled in series, and a plurality of switch circuits 8, which are coupled between the input and output terminals of different buffer circuits 7. The opening and closing of the plurality of switch circuits 8 are controlled by the selection signals SLb0 to SLbn provided from the stage quantity control unit 5.
An input signal IN, which is a clock signal having a similar frequency to the external clock signal CLK, is input to the buffer circuit 7 in the first stage, and an output signal OUT is output from the buffer circuit 7 in the last stage or the switch circuit 8 in the last stage. The phase of the input signal IN does not necessarily have to be the same as the phase of the external clock signal CLK.
The phase adjustment section 2 generates the output signal OUT by delaying the input signal IN by a given phase amount. The digital DLL circuit is mounted on a chip together with an internal circuit that uses the output signal OUT. When the stage quantity control unit 5 outputs the selection signals Sla0 to Slan as the selection signals SLb0 to SLbn without performing any conversions, the delay of the output signal OUT is one fourth of a cycle. The operation for such a basic case will now be described.
The phase adjustment section 2 switches the switch circuits 8 with the selection signals SLb0 to SLbn provided from the stage quantity control unit 5 so that the quantity of the buffer circuits 7 that are coupled is one fourth the quantity of the buffer circuits 3 that are coupled in the phase determination section 1. Therefore, the total quantity of the buffer circuits 7 in the phase adjustment section 2 is one fourth the total quantity of buffer circuits 3 in the phase determination section 1.
In such a configuration, the phase adjustment section 2 generates the output signal OUT delayed from the input signal IN by one fourth of a cycle.
FIG. 3 is a schematic circuit diagram of the delay generation unit 13 in the phase determination section 1. The delay generation unit 13 includes four series-coupled blocks B1 to B4. The blocks B1 to B3 each includes 64 series-coupled buffer circuits (fixed delay elements) 9 specified by addresses 0 to 63. The block B4 does not include a buffer circuit corresponding to address 0 and thus includes 63 series-coupled buffer circuits 9 specified by addresses 1 to 63. Therefore, the delay generation unit 13 includes a total of 255 series-coupled buffer circuits 9. The external clock signal CLK is input to the buffer circuit 9 in the first stage of the block B1, and the delay clock signal CLK-D is provided from the buffer circuit 9 in the last stage of the block B4 to the determination circuit 6.
A switch circuit 10 is coupled in parallel to each buffer circuit 9. Common selection signals SL1 to SL63, which are output from the stage quantity control unit 5, control the opening and closing of the switch circuits 10 in the blocks B1 to B4 that have the same address 1 to 63.
Selection signals SL0a to SL0c independently open and close the buffer circuits 9 of address 0 in each of the blocks B1 to B3.
The selection signals SL0a to SL0c and SL1 to SL63 are generated by decoding the eight-bit phase adjustment signal PC, which is generated by the determination circuit 6. The selection signals SL0a to SL0c are generated from two lower-order bits of the phase adjustment signal PC, and the selection signals SL1 to SL63 are generated from six higher-order bits of the phase adjustment signal PC.
In this case, the delay generation unit 13 opens and closes the switch circuits 10 of addresses 1 to 63 in each of the blocks B1 to B4 based on the six higher-order bits of the phase adjustment signal PC to adjust the quantity of series-coupled buffer circuits 9 in groups of four stages. The delay generation unit 13 opens and closes the switch circuits 10 of address 0 in the block B1 to B3 based on the two lower-order bits of the phase adjustment signal PC to adjust the quantity of series-coupled buffer circuits 9 in groups of single stages and within a range of zero to three stages.
Therefore, the quantity of series-coupled buffer circuits 9 is adjusted by the phase adjustment signal PC in groups of single stages and within a range of 1 to 255 stages.
FIG. 4 shows a specific configuration of the phase adjustment section 2. The phase adjustment section 2 includes 63 series-coupled buffer circuits 11 each having a similar delay time to the buffer circuits 9 of the phase determination section 1. A switch circuit 12 is coupled in parallel to each buffer circuit 11. The input signal IN is input to the buffer circuit 11 in the first stage, and the output signal OUT is output from the buffer circuit 11 or the switch circuit 12 in the last stage.
The stage quantity control unit 5 provides the selection signals SL1 to SL63 to the switch circuits 12. Therefore, the 63 buffer circuits 11 of the phase adjustment section 2 operate in a similar manner to the buffer circuits 9 of addresses 1 to 63 in the blocks B1 to B4 of the phase determination section 1.
With such a configuration, the quantity of series-coupled buffer circuits 11 in the phase adjustment section 2 is the same as the quantity of the selected buffer circuits 9 in the blocks B1 to B4 of the delay generation unit 13. Therefore, the phase adjustment section 2 generates the output signal OUT with a delay of about one fourth of a cycle from the input signal IN when the phase difference between the external clock signal CLK and the delay clock signal CLK-D output from the block B4 is adjusted to one cycle in the phase determination section 1.
In such a digital DLL circuit, the quantity of stages of the buffer circuits 11 of the phase adjustment section 2 is selected by the selection signals SL1 to SL63, which are generated by decoding the six higher-order bits of the phase adjustment signal PC. Therefore, a delay of about one fourth of a cycle is set in the phase adjustment section 2 if a delay of one cycle is set in the phase determination section 1.
However, the adjustment operation in the phase adjustment section 2 does not reflect the quantity of buffer circuits 9 selected by the two lower-order bits of the phase adjustment signal PC in the phase determination section 1. Therefore, when the buffer circuits 11 of the phase adjustment section 2 are selected by the selection signals SL1 to SL63, the quantity of the series-coupled buffer circuits 11 may not be one fourth the quantity of the buffer circuits 9 that are coupled in series in the phase determination section 1.
Therefore, the phase difference of the output signal OUT from the input signal IN is not precisely one fourth of a cycle. In such a case, the generation of jitter in the output signal OUT cannot be reduced.
A digital PLL circuit described in Japanese Laid-Open Patent Publication No. 9-238072 reduces jitter in the output signal by changing the coupled quantity of inverter circuits and the load capacitance to adjust the delay value of a delay variable circuit.
Japanese Laid-Open Patent Publication No. 11-316618 describes a DLL circuit that includes a low-precision phase adjustment circuit and a high-precision phase adjustment circuit and hierarchically operates the phase adjustment circuits. In this publication, the high-precision phase adjustment circuit adjusts the phase by changing the load capacitance.
Japanese Laid-Open Patent Publication No. 11-74783 discloses an internal clock signal generation circuit for finely adjusting the capacitance of a capacitor, which is coupled to a plurality of inverter circuits arranged in a delay line, based on the output signal of a shift register.
Japanese Laid-Open Patent Publication No. 11-205131 discloses a digital PLL circuit for adjusting the delay value in fine widths by controlling delay elements arranged in an oscillator based on a digital control signal output from a delay element control circuit.